Various memory devices have been developed for use as electronic memory media for computers and similar systems. Such memories include electrically erasable programmable read only memory (“EEPROM”) and electrically programmable read only memory (“EPROM”), each of which has advantages and disadvantages. In particular, EEPROM can be easily erased without extra exterior equipment, but has reduced data storage density, lower speed, and higher cost. In contrast, EPROM is less expensive and has greater data storage density, but cannot be easily erased.
A newer type of memory, called Flash EEPROM, or flash memory, has become popular because it combines the high density and low cost advantages of EPROM with the electrical erasability advantages of EEPROM. Flash memory can be rewritten and can retain its contents without consuming power. Flash memory is used in many portable electronic products, such as mobile telephones, portable computers, voice recorders, as well as in many larger electronic systems, such as automobiles, airplanes, and industrial control systems.
An exemplary conventional flash memory device is a charge trapping flash memory device. A charge trapping flash memory device comprises a field effect transistor (“FET”) having a charge trapping layer that is positioned between a control gate and a transistor channel region. The charge trapping layer is electrically isolated by a gate insulator, which is also interposed between the control gate and the channel region. In a conventional configuration, the charge trapping layer and the gate insulator form a oxide-nitride-oxide (“ONO”) stack. The charge trapping layer includes point trapping sites capable of receiving and holding an electron. Generally, the trapping sites have varying trapping energies, or “depths”. The trapping energy is defined as the quantity of energy required to free an electron from a trapping site.
A charge trapping flash memory device can be programmed by the channel hot electron (“CHE”) technique, in which hot electron injection is induced from the channel region, surmounting the gate insulator, to the trapping sites in a charge trapping layer, thereby leading to a nonvolatile negative charge in the charge trapping layer. Electrons trapped in the trapping sites cause a measurable change in the drain current of the transistor. Thus, “charge trapping” in the charge trapping layer forms the basis for the operation of such charge trapping memory devices.